As an element isolation method of semiconductor devices, there is the Deep Trench Isolation (DTI) technology. Compared with the conventional PN junction isolation, the DTI element isolation scheme has the advantage that the device packing can be decreased, while maintaining low leakage characteristics between adjacent devices.
In a semiconductor device, in order to suppress voltage variation in the power supply line, a decoupling capacitor is connected to the power supply line. The variation in the voltage of the power supply line is generated due to the variation in the current flow (draw) of the device elements. Therefore, as a way to suppress voltage variation in the power supply, it would be effective to connect the decoupling capacitor close to the device element that causes the current flow in the power supply line to vary significantly. However, when there are a large number of elements with significant variation in current, the number of decoupling capacitors required to stabilize the voltage also increases.
The semiconductor devices may, for example, incorporate Metal Insulator Metal (MIM) capacitors as the decoupling capacitors. The MIM capacitor is formed by sequentially laminating an insulating layer and a metal layer on an underlying metal layer. Consequently, when a large capacitance is required, the surface area of the capacitor becomes larger. In particular, when a high voltage rated capacitor is required, the insulating layer becomes thicker, and the area of the capacitor becomes even larger.
As a result, when a number of decoupling capacitors are formed in the semiconductor device of 1 chip, the chip area becomes much larger.
Consequently, there is a demand for a semiconductor device where capacitors with high capacitance and high voltage rating can be formed with a small area.